工作职责：

1. Provide detailed block-level design and documents; 2. Develop and execute thorough block level simulation and lab verification plan; 3. Participate in the FPGA platform development and lab debugging; 4. Participate in block level architecture design; 5. Assisting embedded FW development.

任职资格：

1. MSEE; 2. Strong analytical, and problem solving skills as well as hands-on lab debugging skills; 3. Good knowledge of RTL design and simulation; 4. Able to write C code to model RTL blocks for simulation and verification; 5. Able to write reusable Verilog RTL codes, follow design and DFT guidelines; 6. Able to run synthesis, static timing analysis and formal verification is highly desirable, but not required; 7. Knowledge in languages relevant to the ASIC development process including Verilog, System Verilog, Unix Scripting, Perl and Tcl is strong plus; 8. Knowledge of Video/Peripheral/SOC is a plus; 9. Good communication skills, especially in technical writing and reporting; 10. Self-motivated and ability to excel in a team environment.