工作职责：

1. responsible for serdes product architecture definition, critical ip design; 2. take part in serdes product debug/verification, CP/FT test that everything lead to Mass-Production;

任职资格：

1. MSEE with 5 years experiences or above in highspeed interface circuit design, e.g. transmitter/receiver/cdr; 2. hands-on skill in highspeed circuit design; 3. familiar with highspeed circuit related layout knowledge; 4. deep comprehension in highspeed design general theory, e.g. jitter/signal integrity; 5. good team work, self-driven and motivated; 6. experience in serdes architecture definition and critical ip design will be a big plus; 7. thorough experience of full duplex link based serdes’s verification/debug and Mass-Production will be a big plus; 5. practical experience in below pieces will be a plus: 1) full duplex serial link based serdes design; 2) adaptive CTLE/DFE; 3) PI based cdr; 4) LC-PLL; 5) PAM-4 based serdes design; 6) half-rate based serdes design; 7) hands-on Verilog coding skill